In manufacturing semiconductor devices, it is important that the devices are free of defects at the time of production, and reliable throughout their use. When defects are found in a die on a wafer, the percentage of usable die decreases, and the profitability of the manufacturer is impacted. More importantly, when a completed semiconductor device fails after it has been installed in a finished product, such as a consumer electronics product, the failure of the semiconductor device can cause the entire product to fail. That is, the failure of a single semiconductor device can render an entire consumer electronics device unusable. Accordingly, it is important that manufacturers of semiconductor devices identify and eliminate defects whenever possible.
Most semiconductor devices are built up using a number of material layers. Each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete integrated circuit. The patterning process, such as photolithography, defines the dimensions of the circuit features. Modern semiconductor devices have a significant number of layers formed using complex sequences of process steps. Because problems encountered in the formation of any one layer can render an entire device defective, defective devices are therefore tested to physically locate defects. One goal of testing devices is to identify defective layers, which helps to troubleshoot device processes.
Some semiconductor devices, such as field programmable gate arrays (FPGAs) or complex programmable logic device (CPLDs) (collectively known as programmable logic devices (PLDs)), include extensive routing resources. The routing resources are typically collections of parallel metal lines, also commonly called “conductors,” “interconnect lines,” or “interconnects,” formed using overlapping and isolated metal layers. Insulating layers separate the metal layers, enabling the metal lines to comprise interconnect lines between different layers by making contact through “vias” that extend through the insulating layers.
Conventional FPGA interconnect designs typically allow some metal lines in certain layers to be analyzed by components of the circuit. For example, conventional ring oscillator patterns are designed for detecting a defective conductor. A group of failure analysis (FA) test patterns called Metal-FA-Patterns is used to test each specific single metal interconnect layer. The Metal-FA-Patterns are used to monitor the quality of the process to form the physical metal layer by using post process pass/fail results from wafers, and provide quick feedback to process engineers for yield enhancement.
One important element of interconnect designs of an FPGA is a via coupling metal lines on different metal layers. However, conventional ring oscillator patterns are designed for the pass/fail production test environment with no fault localization ability. The ring oscillators tend to use many resources and obtain an average delay time within the conductors under test. Localizing the fault using conventional ring oscillator patterns requires debugging where the extra delay occurs within the design. In addition to taking up much more resources, conventional ring oscillators average out the delays, and therefore do not provide accurate information to determine whether a defect exists in a via.
Accordingly, there is a need for an improved test circuit for and method of detecting a defect in an integrated circuit, and in particular a circuit and method to measure individual interconnect delays across the die to identify specific resistive paths.